Friday, August 26, 2016
VOLUME -27 NUMBER 12
Publication Date: 12/1/2012
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Agilent Intros First Compliance Logic Analysis Test Suite
Real-Time Compliance Application Tool monitors the system under test for the length of time specified for all tests selected.
Santa Clara, CA — Agilent Technologies Inc. has introduced the industry's only test suite for compliance testing of computer and embedded DDR/2/3/4 and LPDDR/2/3 memory applications. With this software suite and an Agilent logic analyzer, digital designers can monitor DDR/2/3/4 or LPDDR/2/3 systems in real time to identify elusive, intermittent violations in protocol or bus-level timing. The new software allows users to customize tests, either by adding to existing test groups or by defining unique test groups of valid logic analyzer triggers for protocol or bus-level timing violations. Customized real-time compliance tests can be defined for any valid logic analyzer trigger, for any digital system probed by an Agilent logic analyzer.

The protocol debug and validation test suite includes three products: B4621B, a bus decoder for DDR/2/3/4; B4622B, a protocol compliance and analysis toolset for DDR/2/3/4 and LPDDR/2/3; and B4623B, a bus decoder for LPDDR/2/3.

The B4621B bus decoder for DDR/2/3/4 debug and validation provides complete protocol decoding of memory transactions using the company's logic analyzer as the execution engine. The protocol-decoding software translates acquired signals into easily understood colorized bus transactions showing associated data bursts for double-edge data-rate captures up to 2.5Gb/s.

The B4622B DDR/2/3/4 and LPDDR/2/3 protocol compliance and analysis toolset is reportedly the industry's only protocol compliance toolset and the first automated, real-time compliance application for DDR4 and LPDDR3. It automatically captures real-time compliance protocol violations, detects post-process protocol violations on captured traces, takes performance measurements, and creates physical address triggers.

The B4623B bus decoder for LPDDR/2/3 debugging and validation is a complete protocol decoder of memory transactions for LPDDR/2/3 using an Agilent logic analyzer as the execution engine. The software translates acquired signals into easily understood bus transactions showing associated data bursts, for all LPDDR2/3 data rates. Valid read and write commands are decoded to include row and column addresses and the complete data burst associated with the command.
Contact: Agilent Technologies, Test and Measurement Organization, 5301 Stevens Creek Blvd., MS 54LAK, Santa Clara, CA 95052 800-452-4844 Web:
http://www.agilent.com

 
 
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