Amkor Unveils High-Performance Flip-Chip Packaging Technology
Sally Cole Johnson, Semiconductor International
Responding to an industry shift toward thinner substrates to improve signal integrity and electrical performance, Amkor Technology Inc. (Chandler, Ariz.) has developed a flip-chip molded ball grid array (FCMBGA) that uses a molded underfill (MUF) rather than a capillary underfill (CUF) — enabling the much-coveted closer spacing between passives and the flip-chip die, better warpage control for thin-core substrates and improved solder joint reliability for passives. 
The new package’s key features include four- to ten-layer buildup substrates, 150 µm minimum bump pitch, die sizes up to 26 mm (with a lid), body sizes from 15 to 50 mm, JEDEC MS-034 compliant, and a 1.0-mm-pitch BGA footprint (Fig. 1).

While Amkor’s advanced molding process technology is considered proprietary, one of the biggest hurdles in its development was that it’s being done in a single-piece substrate format (Fig. 2). “One of the greatest challenges to overcome with this technology, compared to our flip-chip chip-scale package and other offerings that we process in a strip format, was to go in and take single pieces and mold them with the flip-chip die attached,” explained Miguel Jimarez, vice president of flip-chip assembly.
Amkor has been providing the industry with bare (exposed) die flip-chip package structures with capillary underfill, as well as overmolded structures for flip-chip chip-scale package (CSP) requirements. “With a flip-chip CSP, the body size is small, pin counts are low, usually serving handheld applications, assembled in strip form,” noted Lee Smith, vice president of laminate business development. “The flip-chip CSP is molded in an array format that must then be saw-singulated to separate into individual packages. We have been applying the benefits of molded underfill in these applications as well, for both single- and stacked-die combinations.”

Another large hurdle involved doing an exposed configuration on high-pin-count substrates. “It’s more challenging to do this on high-pin-count substrates. The large die has thousands of solder bumps, the silicon is fragile and the gaps for filling are narrow [down to 60 µm],” Jimarez said. “The advantage of leaving the die exposed is that now our customers have the option of putting a lid on it or not — depending on the specific application.”

Vacuum is another important piece of Amkor’s advanced molding process technology. “Because these are very high-pin-count substrates, we needed a good vacuum to be able to fill under the flip-chip die effectively. We needed to integrate this into the single-piece substrate format where we’re leaving the die exposed,” Jimarez explained. “Obviously, you want to avoid problems like voids under the die, mold flash, etc.”

And the mold compound itself was yet another challenge. “We needed a different type of mold compound than the current technologies out there for materials, more similar to a flip-chip underfill,” Jimarez said.

How about reliability? “The drive to thinner substrates can be accomplished using a thinner core. The core essentially supports the substrate and is located at the center of the PCB structure. It provides the rigidity needed to mount the chip on it, underfill and then put BGA balls and a lid on, if you need it. With the core becoming thinner, the rigidity becomes more difficult to maintain package rigidity — especially when you have strict warpage and/or coplanarity specifications to meet,” Jimarez said. “With this technology, we’re able to maintain coplanarity without sacrificing other attributes in terms of finished package requirements. Beyond that, there’s lots of work going on with ultralow-k structures that are more fragile and easily impacted by warpage of the package. By better controlling warpage with this technology, we’re providing the extra reliability needed to maintain integrity for ultralow-k type structures.”

The molded underfill process for these large, high-bump-count die really had to be optimized between the process parameters and mold compound selection because it had to be void-free to meet component reliability requirements and be mechanically optimized to meet the warpage control requirements, Smith pointed out.

Key advantages? “Some other key advantages of the structure are that by eliminating the CUF, we eliminate the underfill fillet and bleed, which allows us to bring decoupling caps much closer to the flip-chip die. That can enhance electrical performance and provide a package size reduction. The industry’s been searching for a good solution to this for years,” Smith said. “This molded underfill technology provides improved design rules because we’ve eliminated the spacing you’d normally require between the die edge and the surface mount component location — because the capillary fillet has been eliminated.”

Where’s the technology headed next? “Right now, we’re doing lots of work with integration,” Jimarez said. “We’re looking at multichip modules for this technology. People are asking us to look at even finer bump pitches and other types of interconnects like copper pillar. Those are the kinds of things coming in the near future for this package platform.”

The new package platform is expected to find applications in a wide array of devices, including ASICs/FPGAs, GPUs and CPUs. “We’re also looking at applications in the mobile market — wireless applications as well as digital TV,” Jimarez said.

And Amkor is seeing a huge spike in demand for flip-chips, especially for wireless applications for cell phones. “In both the RF and baseband sections, there’s been a strong transition to flip-chip for both form factor and electrical performance,” Smith noted. “We saw that trend start at 65 nm with the transition for the digital die — for electrical performance and package form factor reduction. With the 45 nm designs, we expect tremendous transition to flip-chip in that area.”

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